FPGA Based Interfaces
•Xilinx's FPGA Spartan-II XC2S100, plus FPGA boot-PROM
•PCI bus (32 bits/32MHz) with target mode reference design
•USB interface (about 1MBytes/s max sustained)
•Ethernet with 10BASE-T reference design
•I2C master controller, plus onboard I2C EEPROM
•JTAG interface
•8051 microcontroller (on the back of the board). Use of the 8051 is optional. When in use, the 8051 and FPGA can communicate through an 8-bits synchronous bidirectional bus.
•Plug'n play, easy to control from the PC (through the USB)
•program the FPGA boot-PROM
•control the I2C
•PCI bus (32 bits/32MHz) with target mode reference design
•USB interface (about 1MBytes/s max sustained)
•Ethernet with 10BASE-T reference design
•I2C master controller, plus onboard I2C EEPROM
•JTAG interface
•8051 microcontroller (on the back of the board). Use of the 8051 is optional. When in use, the 8051 and FPGA can communicate through an 8-bits synchronous bidirectional bus.
•Plug'n play, easy to control from the PC (through the USB)
•program the FPGA boot-PROM
•control the I2C
Basic PCI FPGA Board
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• Altera Stratix II 60 to 180 FPGA.
• Up to 179400 logic elements.
• PCI Express x4 lanes with full duplex operation.
• 8 DMA channels.
• Five level memory structure (over 4 GB):
•Up to 930 M512 RAM blocks (32 x 18 bits).
•Up to 768 M4K RAM blocks (128 x 36 bits).
•Up to 9 MegaRAM blocks (4K x 144 bits).
• 2 DDR II SODIMMs up to 2GB each. With up to 4.8 GB/s sustain access. (Access of up to 32 ports in parallel).
• Up to 8GB on a PSDB_Mem2. (Access of up to 16 ports in parallel).
• Up to 314 available I/Os.
• Flexible clocking system.
• Typical system frequencies: 100 - 300MHz.
• Up to 179400 logic elements.
• PCI Express x4 lanes with full duplex operation.
• 8 DMA channels.
• Five level memory structure (over 4 GB):
•Up to 930 M512 RAM blocks (32 x 18 bits).
•Up to 768 M4K RAM blocks (128 x 36 bits).
•Up to 9 MegaRAM blocks (4K x 144 bits).
• 2 DDR II SODIMMs up to 2GB each. With up to 4.8 GB/s sustain access. (Access of up to 32 ports in parallel).
• Up to 8GB on a PSDB_Mem2. (Access of up to 16 ports in parallel).
• Up to 314 available I/Os.
• Flexible clocking system.
• Typical system frequencies: 100 - 300MHz.
Basic PCIe FPGA Board
•PCI Express® short form add-in board
•PCI Express® Base Specification 2.0 compliant, tested at 5.0Ghz
•Xilinx Virtex 5 (XC5VFX70T-2FFG1136)
•Standard-based protocols supported
PCI Express 2.0 in Gen2 mode (5.0 GT/sec) in x1 and x4 configurations
PCI Express 2.0 in Gen1 mode (2.5 GT/sec) in x1, x4, x8 configurations
PCI Express 1.1 x1 and x4 Cabling on daughtercard
10/100/1000 Gigabit Ethernet
10 Gigabit Ethernet on daughtercard
•Memory
•128MB DDR2 SDRAM as one bank of 64M x 16-bit
•Up to 2GB DDR2 SDRAM on SODIMM connector
•16MB general purpose Flash memory
•16MB Flash for FPGA configuration
•16MB Flash dedicated for FPGA configuration
•I/O
8 Tx/Rx Gigabits links
13 LVDS signal pairs (13 Rx and 13 Tx)
13 LVDS signal pairs (13 Rx and 13 Tx) or 52 LVCMOS 2.5V signals
100 SSTL2 or LVCMOS 2.5V signals
•Other
•4 x oscillator input
•8x LED
•8x switch
•1x extended RS232
•PCI Express® Base Specification 2.0 compliant, tested at 5.0Ghz
•Xilinx Virtex 5 (XC5VFX70T-2FFG1136)
•Standard-based protocols supported
PCI Express 2.0 in Gen2 mode (5.0 GT/sec) in x1 and x4 configurations
PCI Express 2.0 in Gen1 mode (2.5 GT/sec) in x1, x4, x8 configurations
PCI Express 1.1 x1 and x4 Cabling on daughtercard
10/100/1000 Gigabit Ethernet
10 Gigabit Ethernet on daughtercard
•Memory
•128MB DDR2 SDRAM as one bank of 64M x 16-bit
•Up to 2GB DDR2 SDRAM on SODIMM connector
•16MB general purpose Flash memory
•16MB Flash for FPGA configuration
•16MB Flash dedicated for FPGA configuration
•I/O
8 Tx/Rx Gigabits links
13 LVDS signal pairs (13 Rx and 13 Tx)
13 LVDS signal pairs (13 Rx and 13 Tx) or 52 LVCMOS 2.5V signals
100 SSTL2 or LVCMOS 2.5V signals
•Other
•4 x oscillator input
•8x LED
•8x switch
•1x extended RS232
Advanced PCIe FPGA Board
•Xilinx Virtex 5 in an FF1136 package. Supports LX50T/LX85T/SX50T or LX110T/SX95T.
•FPGA configuration from 64MByte flash using a Xilinx Coolrunner CPLD.
•One 64-bit wide data bank of DDR2 memory. The bank uses 4 16-bit wide devices. Running this memory at 220MHz provides a maximum access speed of over 3.5Gbyte/s.
•LVDS Bus connector.
•Front panel SATA connectors carrying Virtex5 serial interfaces.
•Front panel RJ45 for gigabit Ethernet.
•Front panel Fibre Optic modules carrying Virtex5 Serial interfaces.
•RSL connector with 4 serial interfaces.
•On-board USB interface to allow re-programming of the flash memory.
•FPGA configuration from 64MByte flash using a Xilinx Coolrunner CPLD.
•One 64-bit wide data bank of DDR2 memory. The bank uses 4 16-bit wide devices. Running this memory at 220MHz provides a maximum access speed of over 3.5Gbyte/s.
•LVDS Bus connector.
•Front panel SATA connectors carrying Virtex5 serial interfaces.
•Front panel RJ45 for gigabit Ethernet.
•Front panel Fibre Optic modules carrying Virtex5 Serial interfaces.
•RSL connector with 4 serial interfaces.
•On-board USB interface to allow re-programming of the flash memory.
Basic PXIe FPGA Board
• DSP-focused Virtex-5 SX95T FPGA
•512 MB onboard DDR2 DRAM
•Access to 132 single-ended I/O lines, configurable as 66 differential pairs
•Customizable I/O with Adapter Module Development Kit
• 16 DMA channels for high-speed data streaming at more than 800 MB/s
• Peer-to-peer data streaming to and from other FPGA modules
•512 MB onboard DDR2 DRAM
•Access to 132 single-ended I/O lines, configurable as 66 differential pairs
•Customizable I/O with Adapter Module Development Kit
• 16 DMA channels for high-speed data streaming at more than 800 MB/s
• Peer-to-peer data streaming to and from other FPGA modules
Advanced PXIe FPGA Board